1. Field of the Invention
This invention relates generally to digital logic systems and more specifically to a clock synthesizer system and method therefor which uses a plurality of dual function pins to apply a frequency selection code while in a first operating mode and to transmit a buffered clock signal while in a second operating mode to obtain a reduced pin count for the system.
2. Description of the Prior Art
In effective and cost efficient designs for digital systems and, in particular, in designs based on integrated circuit (IC) microprocessors, it is advantageous to reduce the number of IC package terminals or "pins" to as small a number as possible. This is a desired objective because of several key factors: (1) an IC design which minimizes the number of electrical paths on and off the chip will tend to have a reduced chip area and therefore a lower chip manufacturing cost, (2) a reduced number of electrical paths on and off the IC chip will correspondingly reduce the size and pin count of the package or module used to contain the chip which will reduce the cost of both the package or module itself and the cost of assembling it, and (3) a physically smaller reduced pin-count package will create additional available space and interconnection opportunities on the printed circuit board to which it is mounted. The resulting additional available circuit pins and the associated added layout "real estate" allows the digital systems manufacturer to provide additional system functions without the step function cost increase that would otherwise be required by an additional printed circuit board.
One category of digital sub-systems which often particularly benefits from additional available circuit pins is frequency selectable clock synthesizer systems. These systems are widely used in microprocessor applications where one master system board (often called a "mother board") is reconfigured to adapt to different members of a family of computers. A key element of the reconfiguration is the use of a specific set of electrical conditions on a set of input pins called "frequency select pins". Thus, for example, the electrical conditions established on a set of four frequency select pins at the time a specific motherboard was configured could be used to set one of 16 possible clock frequencies such that the specified frequency is appropriate for the particular microprocessor chip and the other components of that motherboard. A significant disadvantage of this approach is that although a plurality of frequency select pins must be dedicated and available to define the possible required clock frequencies, these pins are only used once at the time the clock synthesizer is configured. Although they are dormant, they are not available for other functions.
Thus a need exists for an improved clock synthesizer design which accomplishes frequency selection in a simple, pin conserving and cost effective manner.